The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to redundancy selection in non-volatile semiconductor memory devices and associated circuitry for providing test inputs.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Redundancy is a method of incorporating spare or redundant devices on a semiconductor die that can be used to replace defective devices. Redundancy is widely used in high density memory devices to improve production yield. As an example, a memory device may have redundant elements, such as redundant memory cells, redundant rows of memory cells or redundant columns of memory cells. If a primary element is determined to be defective, the defective element may be replaced by a redundant element by redirecting the address of the defective element to the redundant element in a manner known in the art. By replacing the defective element, an otherwise unusable memory device becomes commercially acceptable. Redundancy generally introduces additional complexity and speed delay to the memory device.
During manufacturing testing of the memory device, it may be desirable to temporarily enable one or more of the redundant elements in response to one or more test input signals. Such temporary enabling typically involves the introduction of test input signals into the redundancy selection path. Providing for temporary enabling of a redundant element generally entails additional logic to process the test input signals. It is desirable that such enabling logic not introduce additional speed delay to the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate integrated circuits to facilitate selection of redundant elements in semiconductor memory devices while providing for temporary enabling of such redundant elements during manufacturing testing of the memory device.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Memory devices having redundancy selection circuitry are described herein, with particular reference to synchronous non-volatile memory devices. The memory devices include a redundancy selection circuit having a latch for latching an incoming redundancy match signal. The latch includes a pair of reverse-coupled inverters. The latch is further coupled to receive one or more test input signals. The latch is responsive to one or more control signals to selectively generate the latched match signal from the incoming redundancy match signal or one of the test input signals. When the latched match signal is generated from incoming redundancy match signal, the logic level of the latched match signal is independent of the logic level of any of the test input signals. When the latched match signal is generated from one of the test input signals, the logic level of the latched match signal is independent of the logic level of the incoming redundancy match signal. Such latch circuits are useful for controlling selection of a redundant element in a memory device during testing without significantly impacting the speed path of the redundancy selection circuitry during normal operation of the memory device.
For one embodiment, the invention provides a method of operating a memory device. During a test mode, the method includes applying a first input signal to an input of a latch; latching the first input signal in the latch, thereby generating a first latch output signal from the first input signal; applying a control signal to the latch to introduce a test input signal into the latch, thereby generating a second latch output signal from the test input signal, wherein the second latch output signal is independent of a logic level of the first input signal; accessing a primary element when the second latch output signal has a first logic level; and suppressing access to the primary element when the second latch output signal has a second logic level. During a normal operation, the method includes comparing an applied memory cell location address with a known defective address; generating a redundancy match signal indicative of whether the applied location address matches the known defective address; applying the redundancy match signal to the input of the latch; latching the redundancy match signal in the latch, thereby generating a third latch output signal, wherein the third latch output signal has either the first logic level or the second logic level, the first logic level being indicative of a match between the applied location address and the known defective address; accessing a primary element associated with the applied location address when the third latch output signal has the second logic level; and suppressing access to the primary element associated with the applied location address when the third latch output signal has the first logic level.
For another embodiment, the method includes a method of operating a memory device. The method includes applying a first input signal to an input of a feedforward inverter; inverting the first input signal, thereby generating a first feedforward signal on an output of the feedforward inverter; isolating the first input signal from the feedforward inverter; applying the first feedforward signal to a first input of a feedback inverter; inverting the first feedforward signal, thereby generating a first feedback signal on an output of the feedback inverter; applying the first feedback signal to the input of the feedforward inverter; inverting the first feedback signal, thereby generating a second feedforward signal on the output of the feedforward inverter; applying the second feedforward signal to the first input of the feedback inverter and applying a test input signal to a second input of the feedback inverter; generating a second feedback signal from the test input signal, wherein the second feedback signal has a logic level independent of a logic level of the second feedforward signal; applying the second feedback signal to the input of the feedforward inverter; inverting the second feedback signal, thereby generating a third feedforward signal on the output of the feedforward inverter; and selectively accessing either a primary memory element or a redundant memory element in response to a logic level of the third feedforward signal.
For yet another embodiment, the invention provides a method of testing a memory device. The method includes applying a first input signal to a first input of a feedforward inverter; inverting the first input signal, thereby generating a first feedforward signal on an output of the feedforward inverter; isolating the first input signal from the feedforward inverter; applying the first feedforward signal to an input of a feedback inverter; inverting the first feedforward signal, thereby generating a first feedback signal on an output of the feedback inverter; applying the first feedback signal to the first input of the feedforward inverter and applying a test input signal to a second input of the feedforward inverter; generating a second feedforward signal from the test input signal, independent of a logic level of the first feedback signal; and selectively accessing either a primary memory element or a redundant memory element in response to a logic level of the second feedforward signal.
The invention further provides methods of varying scope.